(1)Field of the Invention
The present invention relates to a memory apparatus using a microprocessor and a memory device and in detail, relates to a memory apparatus for storing numbers or data such as apparatus numbers and key numbers for descrambling which are different for every apparatus used in, for example, receivers for scrambled broadcast.
(2)Description of the Prior Art
Recently, scrambled broadcast utilizing broadcast satellites and communication satellites started and have spreaded in which only receivers which fulfill a particular condition can descramble and display a normal picture.
A memory apparatus used in scrambled broadcast in accordance with the prior art is explained below referring to FIG. 1.
In FIG. 1, a microprocessor 1 outputs address signals 5 and 6 for controlling peripheral equipments such as an address decoder 2 for memory selection and a memory device 3 which is able to write and read, a write enable signal 12a (WE signal, hereafter) and a read enable signal 11a (OE signal, hereafter) and has a data bus between a memory device 3. The memory device 3 accepts a chip select signal 13 (CS signal, hereafter) which makes possible to access the memory device 3, address signal 6 necessary for indicating an entire area in the memory device 3, WE signal 12a and OE signal 11a. Microprocessor 1 and memory device 3 are connected by a data bus 4. An address decoder 2 for memory selection is supplied with address signal 5, outputs CS signal 13 and CS signal 13 is supplied to memory device 3. The performance of the memory apparatus configurated as above is explained below referring to FIG. 1. For simplification of explanation, it is assumed that the memory capacity of memory device 3 is 256 addresses and microprocessor 1 outputs 12 address signals but they are not restricted to the above figures. The address signals are expressed by A11 to A0, address signals 5 share the upper addresses of 4 bits, address signals 6 share the lower addresses of 8 bits and the address area is expressed by hexadecimal numbers.
Lower address signals 6 expressed by A7 to A0 are directly inputted to memory 3 and upper address signals 5 expressed by A11 to A8 are inputted to memory 3 through address decoder 2 for memory selection as CS signal 13.
Here, for instance, the address area of memory device 3 is defined as 300 to 3FF. Therefore, address decoder 2 for memory selection is an address decoder which becomes an "enable" level when address signals 5 composed of four address signals, A11 to A8, is 0011 (in binary number), i.e. 3 (in decimal number). Accordingly, when the address signals A11 to A0 outputted from microprocessor 1 are 300 to 3FF, CS signal 13 inputted to memory device 3 becomes "enable". In this state, the data is read from memory device 3 when RE signal 11a is "enable" and the data is written in memory device 3 when WE signal 12a is "enable".
The numbers or the data which are different for every apparatus such as apparatus numbers of receivers for scrambled broadcast and key numbers for descrambling are unnecessary to rewrite if they are once stored. If they are rewrite, the receivers can not correctly perform.
In the above configuration in accordance with the prior art, however, there is a problem that there is high possibility in false rewriting of necessary data due to misoperation at writing, run away of microprocessor or noise.